The present relates to a semiconductor integrated circuit device, and more particularly to effective technology to be applied to a semiconductor integrated circuit device adopting a master slice system.
A gate array is a typical example of a semiconductor device adopting a master slice system. The gate array is provided with a plurality of basic cells arranged regularly in matrix form on a semiconductor substrate, and connection is performed in each basic cell and between basic cells by plural layers of wiring. Each basic cell of the gate array developed by the present inventor has bipolar transistors and complementary MOSFETS. A semiconductor integrated circuit device adopting such master slice system can constitute various logic circuits by only changing the wiring patterns in each basic cell and between basic cells. In other words, the semiconductor integrated circuit device is characterized in that various sorts of LSI can be developed in a short period.
In the semiconductor integrated circuit device adopting the master slice system, the wiring patterns to perform connection in each basic cell and between basic cells respectively are determined by the automatic arrangement and routing system of design automation (DA or CAD : Computer Aided Design) using a computer. The automatic arrangement and routing system receives logic connection information (wiring information) prepared based on logic specification of LSI to be produced and has the function of automatically generating (producing) the wiring pattern to perform connection in each basic cell and between basic cells respectively in X-Y lattice-shaped wiring channel region. The X-Y lattice-shaped wiring channel region is a wiring channel region set imaginarily (temporarily) in the memory space of the automatic arrangement and routing system. The X-Y lattice-shaped wiring channel region is composed of a plurality of the X wiring channel regions with signal wirings of the first layer extended imaginarily in the X direction and of a plurality of Y wiring channel regions with signal wirings of the second layer extended imaginarily in the Y direction respectively arranged in lattice form. Each lattice point of the X-Y lattice-shaped wiring channel region is used as a connection position for connecting signal wirings of the first and second layers to each other or a connection position for connecting an input/output terminal of a basic cell to the signal wiring.
In such semiconductor integrated circuit device adopting the master slice system, since all usable wiring paths are clearly defined as the X-Y lattice-shaped channel region, processing function of the software of the automatic arrangement and routing system can be simplified thereby the semiconductor integrated circuit device is suitable for the design automation.
According to the automatic arrangement and routing system, the wiring pattern information automatically generated in the X-Y lattice-shaped wiring channel region becomes information for generating a manufacturing mask to be used in the manufacturing process. According to the manufacturing mask generated by the information, each of the actual signal wirings formed on the semiconductor wafer (basic chip) has the wiring width or the wiring film thickness previously determined in consideration of the current capacity of the signal wiring or electromigration.
If the manufacturing mask is generated, the LSI manufacturing process (device process) is performed using the manufacturing mask. The LSI manufacturing process is processing where signal wirings are needed to perform connection in each of a plurality of basic cells previously formed and between the basic cells on the semiconductor wafer (basic chip). An aluminum wiring is used as the signal wiring.
A semiconductor integrated circuit device adopting the master slice system with basic cells constituted by bipolar transistors and complementary MOSFETs is disclosed, for example, in Denshi Zairyo (Electronic Material) July 1987, pp. 49-52, published by K. K. "Kogyo Chosakai".
Also Japanese patent application laid-open No. 182540/1984 discloses technology in a semiconductor integrated circuit device adopting the master slice system wherein an exclusive channel is allocated for a wiring pattern connecting between terminals of a basic cell relatively remote among a plurality of basic cells formed previously on a semiconductor wafer, or for a clock signal wiring pattern whereby delay is decreased in the logic. The laid-open application also discloses that in order to make the effect as the exclusive channel larger, the width of the wiring pattern allocated on the exclusive channel may be made wider than that of the wiring pattern allocated on other ordinary channels.